(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of improving yield in a damascene method in the manufacture of integrated circuits.
(2) Description of the Prior Art
In a common application for integrated circuit fabrication, a contact/via opening is etched through an insulating layer to an underlying conductive area to which electrical contact is to be made. A conducting layer material is deposited within the contact/via opening. The damascene and dual damascene processes have become a future trend in metallization. Trenches or vias and trenches are etched in an insulating layer. The trenches or vias and trenches are inlaid with metal to complete the contacts. It is desired to use low dielectric constant (low-k) materials in order to reduce capacitance of the resulting devices. Silicon carbide (SiC) or silicon nitride (SiN) is widely used to improve adhesion when using organic low-k materials in the intermetal dielectric layers (IMD). To avoid micro-scratching during the final polishing metal step, a minimal amount of the low-k material should be polished. To accomplish this, a polish stop layer is provided over the low-k material. The use of SiC, SiN, or silicon oxynitride (SiON) as the polish stop layer will cause a problem at the pre-metal deposition step. After the trench has been etched through the IMD layer, an Ar sputtering cleaning step is performed. The polish stop layer, which is the topmost layer of the IMD layer, will be exposed to the Ar sputtering. The sputtering chamber walls are typically composed of quartz (SiO.sub.2). Adhesion between the SiON and quartz is poor, resulting in peeling of the SiON on the chamber walls due to thermal stress from wafer to wafer processing. Particles generated from this peeling will undesirably contaminate the wafer. It is desired to find a IMD scheme that will avoid the particle issue and hence lead to yield improvement.
U.S. Pat. No. 6,100,181 to You et al discloses a dual damascene process. U.S. Pat. No. 6,083,850 to Shields uses HSQ, a low-k material, as a gap-filling layer. U.S. Pat. Nos. 5,891,799 to Tsui and 5,858,870 to Zheng et al teach non-damascene IMD schemes. U.S. Pat. No. 6,071,809 to Zhao shows a dual damascene process using a silicon nitride polish stop layer with an overlying protection layer. Preferably, the protection layer is silicon dioxide, but it may also be silicon oxynitride or other materials that will cause particle problems.